NXP Semiconductors /MIMXRT1062 /IOMUXC /SW_MUX_CTL_PAD_GPIO_B0_02

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SW_MUX_CTL_PAD_GPIO_B0_02

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

MUX_MODE=ALT0, SION=DISABLED

Description

SW_MUX_CTL_PAD_GPIO_B0_02 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: LCD_HSYNC of instance: lcdif

1 (ALT1): Select mux mode: ALT1 mux port: QTIMER1_TIMER2 of instance: qtimer1

2 (ALT2): Select mux mode: ALT2 mux port: FLEXCAN1_TX of instance: flexcan1

3 (ALT3): Select mux mode: ALT3 mux port: LPSPI4_SDO of instance: lpspi4

4 (ALT4): Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO02 of instance: flexio2

5 (ALT5): Select mux mode: ALT5 mux port: GPIO2_IO02 of instance: gpio2

6 (ALT6): Select mux mode: ALT6 mux port: SEMC_CSX03 of instance: semc

8 (ALT8): Select mux mode: ALT8 mux port: ENET2_1588_EVENT0_OUT of instance: enet2

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_B0_02

Links

() ()